1. Technical Field
The present invention relates to semiconductor technology, and, particularly, to a process of forming self-aligned silicides on a MOS device.
2. Description of Related Art
As device dimensions approached 1 micrometer, the conventional contact structures used up to that point began to limit device performance in several ways. For example, the device contact resistance is larger when the area of the source/drain regions is reduced. A variety of contact structures have been investigated to alleviate the above problem. One is self-aligned silicides on the source/drain regions. (When these silicides are formed at the same time as the polycide structure, the approach referred to as a salicide process). The other is raised source/drain regions (formed by Si deposition onto the exposed source/drain regions).
Raised source/drain engineering using selective epitaxial Si (epi-Si) growth has become important recently. This technology not only provides more Si for better salicidation, but also prevents the consumption of substrate silicon during the salicide process. Therefore, low leakage current (resulting from no substrate consumption) can be obtained, which is especially useful for shallow junction applications. However, as shown in FIG. 1, when selective epi-Si 102 is used to form source/drain (S/D) regions 104, pre-amorpharization implant (PAI) hardly reaches the substrate 100. As a result, silicides 106 are formed only above Si-substrate 100 and is separated from the lightly doped drains (LDDs) 108 by a distance 110. This distance 110 causes a region having high series resistance (R.sub.s) and low drain current (I.sub.dsat) between the silicides 106 and the LDDs 108.